Circuit for testability

Abstract

An evaluation facilitating circuit incorporated in a logic circuit having a plurality of functional blocks, includes: many scan register groups obtained by dividing many F/Fs provided in each functional block, many scan paths for scanning a plurality of test data used for input and output operations for the scan register groups, wherein a scan path is provided for each scan register group, and a decoder for designating the scan paths and controlling the input and output operations of test signals used for testing the scan register groups. A first scan register group in each functional group is composed of scan registers only used for the input operations to other functional blocks, a second scan register group is composed of scan registers only used for the output operations to other functional blocks and a third scan register group is composed of scan registers used for the input and output operations to the same functional block. Each scan path is connected to a common bus provided in the functional circuit. The common bus includes many signal lines through which the test data is transferred, and the scan path connected to a first scan register group is connected to a first pair of signal lines, the scan path connected to the second scan register group is connected to a second pair of signal lines, and the scan path connected to the third scan register group is connected to a third pair of signal lines.