The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 1992
Filed:
Mar. 20, 1990
Takeshi Kajimoto, Hamura, JP;
Yutaka Shimbo, Hino, JP;
Katsuyuki Sato, Akishima, JP;
Masahiro Ogata, Fussa, JP;
Kanehide Kenmizaki, Kodaira, JP;
Shouji Kubono, Akishima, JP;
Nobuo Kato, Ohme, JP;
Kiichi Manita, Kawagoe, JP;
Michitaro Kanamitsu, Akishima, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi VLSI Engineering Corp., Kodaira, JP;
Abstract
A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates.