The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1992

Filed:

May. 09, 1991
Applicant:
Inventors:

Akira Ito, Kunitachi, JP;

Yoichi Sato, Iruma, JP;

Tosiyuki Ohkuma, Ohme, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
365201 ; 365154 ; 365156 ; 365226 ; 365218 ; 371 211 ; 371 214 ;
Abstract

A static random access memory (RAM) includes a data set circuit (DSC) coupled to pairs of load elements of memory cells to test the connection between a pair of load elements and a pair of memory nodes of each of the memory cells. The data set circuit responds to predetermined control signals and data to be set to the memory cells and supplies the predetermined voltage corresponding to such data to the pair of load elements. If the pair of load elements and the memory nodes of a memory cell are properly coupled, data of the memory cell will be inverted. Therefore, if the data of a memory cell is not inverted during the test, it can be quickly determined that a disconnection fault exists at that memory cell location.


Find Patent Forward Citations

Ito, Akira. (1992). Semiconductor memory with a circuit for testing characteristics of (U.S. Patent No. 5159571). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5159571

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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