The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1992

Filed:

Nov. 27, 1990
Applicant:
Inventors:

Kishan Shenoi, Milpitas, CA (US);

David J Wetle, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; G06F / ;
U.S. Cl.
CPC ...
328109 ; 328110 ; 307527 ; 307528 ; 307234 ; 307471 ; 331 / ; 331 27 ;
Abstract

A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.


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