The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 1992
Filed:
Nov. 20, 1990
Toshiyuki Yaguchi, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
Disclosed is a test facilitating circuit which is incorporated in an LSI system having a plurality of master modules and a plurality of slave modules, a common bus for connecting the master modules and the slave modules, and a bus arbiter for adjusting use of the common bus. The test circuit utilizes tri-state buffers and control lines for prohibiting transmission of an acknowledgement signal from the bus arbiter to a master module to be tested among the plurality of master modules in a test mode. The test circuit inputs an acknowledgement signal generated from the master module, and which outputs it to the slave modules. An AND gate is used for masking acknowledgement signals to be transmitted from the bus arbiter to master modules other than the master module to be tested. A test I/O bus is used (comprising control lines and data lines) for carrying out initial setting to a memory portion in the master module to be tested, and reading data stored in the memory portion; and an ordinary operation control line sets the master module and the slave modules into an ordinary operation mode.