The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1992

Filed:

Nov. 30, 1990
Applicant:
Inventor:

Toshikazu Fujii, Kanagawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307494 ; 307351 ; 307362 ;
Abstract

An extreme level circuit for detecting an extreme level of two input signals. The circuit includes a differential circuit wherein a pair of differential transistors are connected their emitters with each other and a common current source is connected to the emitter junction node of the differential transistors, a pair of emitter follower transistors coupled to the differential circuit for applying the input signals to the bases of the differential transistors and a pair of bias generating circuits each coupled in series with one of the emitter follower circuits, wherein each bias generating circuit has a bias transistor whose base is connected to a fixed bias source and a current source connected in series with the bias transistor, and wherein the pair of bias generating circuits are cross connected to the collectors of the differential transistors.


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