The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1992

Filed:

Sep. 30, 1991
Applicant:
Inventors:

Yasunobu Kosa, Austin, TX (US);

W Craig McFadden, Austin, TX (US);

Keith E Witek, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437 29 ; 437 35 ; 437 41 ; 437 59 ; 437 89 ; 437913 ; 148D / ;
Abstract

A field effect transistor having regions (20, 20', and 20') which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20'), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20') and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34', 34', and 34, respectively).


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