The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 1992
Filed:
Oct. 18, 1991
Chi-Kwan Lau, Saratoga, CA (US);
Donald L Packwood, San Jose, CA (US);
Chen-Hsi Lin, Cupertino, CA (US);
Ashor Kapoor, Palo Alto, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A method of fabricating a BiCMOS device in which PMOS and NMOS transistors are formed prior to a base/emitter structure of a bipolar transistor. In forming the base/emitter structure, a blanket implant of a first impurity is introduced into a base region of a semiconductor substrate. An insulating layer is deposited and then patterned to expose a portion of the base region at an emitter window. A polysilicon layer is deposited on the insulating layer and into the emitter window. The polysilicon layer is patterned to provide the desired configuration at the emitter window, whereafter the remaining polysilicon acts as a mask for etching of the insulating layer. Thus, etching of the insulating layer is performed in a self-aligning manner. Self-alignment is also utilized in providing a base-link region and in providing a silicide layer.