The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 1992
Filed:
Sep. 21, 1989
Harold C Waite, Garland, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An offline redundancy memory test system replaces fail memory equipment, under the control of a test system CPU, with fail memory equipment under the control of a second CPU. The second CPU is dedicated to the analysis of the contents of the offline redundancy memory test system fail memory, for redundancy identification and defect pattern analysis, at the conclusion of functional testing. Therefore, in a mass production wafer level memory test system, the test system CPU is free to prepare and execute non-functional tests on the next set of devices to be tested, thereby reducing overall memory test time by the amount of fail memory equipment analysis time previously taken by the test system CPU leading to a reduction in the total number of memory test systems required to provide redundancy memory testing.