The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 1992

Filed:

Mar. 18, 1991
Applicant:
Inventor:

Robert G Crick, San Diego, CA (US);

Assignee:

Tempo Research, Vista, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
324613 ; 324612 ; 324523 ; 324512 ;
Abstract

A device for measuring and isolating noise-creating imbalances in a paired telecommunications line has an internal circuit which includes a pair of substantially balanced ac current outlet pathways in parallel, a differential amplifier connected to a pair of voltage inlet pathways, and an oscillator to supply longitudinal alternating current to the paired line across the balanced pathways. A longitudinal alternating current signal is sent from the oscillator to each conductor of the line across the outlet pathways, travels the length of each conductor and returns to the inlet pathways as a metallic voltage signal. If there is any imbalance between the two conductors, the metallic voltage signals for the two conductors will be different. Accordingly, the differential amplifier measures this difference and it is displayed in units of noise or balance. The outlet pathways further function to minimize the amount of dc loop current drawn from the paired line and a ground pathway is provided to substantially minimize low frequency ac power influence current flow to ground. The oscillator supplies alternating current for testing, so the device does not use the dc current of the loop being tested and is, therefore, applicable to testing either wet or dry paired lines.


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