The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 1992
Filed:
Aug. 28, 1990
Fazal Ali, Santa Clara, CA (US);
Allen F Podell, Palo Alto, CA (US);
Pacific Monolithics, Sunnyvale, CA (US);
Abstract
A double-.pi. network includes a pair of series resistors connected between input and output terminals. A plurality of FETs of different widths and/or in series with resistors, are each connected in parallel with one of the series resistors. Each FET is controlled jointly with an FET of the same gate size associated with the other series resistor, so that select ones of the FETs, or none may be conducting in parallel with the series in-line resistances. Another plurality of intermediate FETs having gates with different widths, are connected in parallel and separately controllable for coupling selectively the junction between the two in-line resistors to ground. Finally, an additional plurality of pairs of FETs couple the input and output terminals to ground. The FETs making up each pair have gates with the same width and are jointly controllable. The FETs in the different pairs have different widths and/or are in series with different sized resistors. By controlling operation of the FETs, different attenuation configurations, such as .pi., T, and double-.pi., are produced as well as different discrete attenuation levels.