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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5155570 B1

PDFFull Text
Date of Patent:
Oct. 13, 1992

Filed:

Jan. 25, 1991

Semiconductor integrated circuit having a pattern layout applicable to

Applicant:
Inventors:

Kazuo Tomizuka, Gunma, JP;

Sakae Sugayama, Gunma, JP;

Takao Saeki, Gunma, JP;

Toshiaki Imai, Gunma, JP;

Assignee:

Sanyo Electric Co., Ltd., Osaka, JP;

Attorney:

Darby & Darby

Primary Examiner:

Rolf Hille

Assistant Examiner:

Steven Loke

Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 40 ; 357 41 ; 357 45 ; 357 47 ;
Abstract

A semiconductor integrated circuit is formed on a semiconductor chip (1) and it includes: a plurality of mat regions (A to T) each including a plurality of circuit elements (10 to 13); partition regions (4) for spacing the mat regions (A to T) from each other; and a pair of power supply line (2) and ground line (3) disposed on each of the partition regions (4). An electronic circuit formed on the semiconductor chip (1) includes circuit blocks having different functions but it is designed for a unit of each mat (A to T) not for a unit of each circuit block.

Find Patent Forward Citations

Tomizuka, Kazuo. (1992). Semiconductor integrated circuit having a pattern layout applicable to (U.S. Patent No. 5155570). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5155570

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