Logic gates with controllable time delay

Abstract

Apparatus for introduction of a controllable time delay in the transition of a logic device output signal from a first logical level to a second logical level, in response to change of an input signal, or the difference of two input signals from a third logical level to a fourth logical level, delivered to the logic device. In a first embodiment, a limiting amplifier receives an input signal S.sub.in and a threshold signal V.sub.T at its two terminals and forms an amplified difference output signal S.sub.out. A selected voltage level signal V.sub.L and S.sub.out are received at a signum function module and the output signal sgn(S.sub.out -V.sub.L) is formed and issued. The signum output signal is multiplied by a controllable real number m and is added to V.sub.L to form the threshold signal V.sub.T. The desired output signal S.sub.out makes a transition between the first and second logical levels, with a time delay that is controllable by choice of the number m. In a second embodiment, which also uses a signum function, two input signals, S.sub.in,1 and S.sub.in,2, give rise to two output signals, S.sub.out,1 and S.sub.out,2, and the difference signal S.sub.out,1 -S.sub.out,2 makes a transition between two logical levels with a time delay that depends controllably on choice of the number m.