Arithmetic processor using signed digit representation of internal

Abstract

This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.