Ttl output buffer with temperature compensated v.sub.oh clamp circuit

Abstract

A V.sub.OH clamp circuit reduces propagation delay time TP.sub.HL and reduces ground bounce noise in TTL output buffer circuits. First and second band gap bias generators (BG1,BG2) coupled in series provide a substantially stable clamp reference voltage level (V.sub.R) over a specified range of operating temperatures. The clamp reference voltage level (V.sub.R) is referenced to the low potential power rail (GND). Voltage drop components (D32,QC) of the Y.sub.OH clamp circuit couple the reference voltage level (V.sub.R) through the voltage drop components (D32,QC) to an internal node, namely the base node (BDAR) of the pullup Darlington configuration transistor pair (Q12A,Q12B), The V.sub.OH clamp circuit clamps the high potential level output signal (V.sub.OH) at a maximum voltage level (V.sub.OHMAX) less than the high potential level power rail (V.sub.cc), and referenced to the clamp reference voltage level (V.sub.R). The band gap bias generator circuit (BG1,BG2) establishes a substantially stable clamp reference voltage level (V.sub.R) approximately equal to the output signal maximum voltage level (V.sub.OHMAX). The V.sub.OH clamp circuit voltage drop components (D32,QC) establish a step up voltage drop approximately equal to the step down voltage drop across the pullup Darlington transistor pair (Q12A,Q12B).