Microcomputer system with selectively bypassed memory output latches

Abstract

A microcomputer system includes a memory storing various processing data including instruction codes, and a data processor for executing an instruction. The memory includes an address pointer for indicating an address for the memory and supplying the stored address to the memory, and an incrementer for incrementing the address pointer. A latch is coupled to the memory for holding an output of the memory read out in accordance with the address supplied from the address pointer. A bus interface is provided for controlling the address pointer and the incrementer so as to cause a one-time transfer to be performed between the memory and the data processor after an address is supplied from the data processor to the address pointer. The bus interface also controls the address pointer, the incrementer and the latch so that the latch holds contents which are read out from the memory at the address supplied by the address pointer, and the incrementer to increment the address pointer, whereby a continuous transfer is realized between the memory and the data processor without continuously supplying addresses from the data processor.