The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1992
Filed:
Jan. 31, 1990
Yoshinori Nishiyama, Odawara, JP;
Tomoatsu Yanagita, Ebina, JP;
Masahiko Nagai, Kanagawa, JP;
Mitsuru Morikuni, Ebina, JP;
Kenji Matsumoto, Kanagawa, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Computer Engineering Co., Ltd., Kanagawa, JP;
Abstract
A signal line terminal allocation method includes an electronic device which is hierarchically designed to obtain terminal allocations which satisfy electrical restrictive conditions. The electronic device includes high hierarchial components and low hierarchial components; the high hierarchial components are connected to the low hierarchical components by a plurality of signal lines through a plurality of signal line terminals. The method including the steps of: 1) obtaining all the different combinations of an allocation of the signal lines to the signal line terminals; 2) calculating a plurality of signal line lengths for all the different combinations, each of the plurality of signal line lengths corresponding to a sum of the line lengths of each of the signal lines in the allocation; and 3) selecting the combinations of allocation of signal lines in which electrical restrictions corresponding to each of the plurality of signal lines are satisfied, the electrical restrictions including the maximum line length. The above method includes groups of plural signal lines of both high and low hierarchial components.