The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1992
Filed:
Mar. 25, 1991
Ming-Zen Lin, Hsinchu, TW;
Industrial Technology Research Institute, Chutung, TW;
Abstract
A buffer circuit for connecting a CMOS logic circuit to receive TTL logic level signals assures that the upper and lower FET's of an otherwise conventional input inverter stage do not both turn on together in the situation in which an input signal has a level that is high enough to turn on the lower FET but not high enough to turn off the upper FET. A third and a fourth FET are connected to form a controlled power supply stage that controls the current supplied to the upper FET. The third FET has its gate connected to be controlled from the output of a second inverter stage (which is in phase with the input to the first stage). When the TTL input rises, the second inverter stage output turns off the third FET and thereby turns off the upper FET. The fourth FET is connected as a capacitor that is charged while the third FET is turned on and then supplies current to switch the output inverter stage when the upper FET is turned on. A fifth FET is connected to charge the capacitor and a circuit is provided to detect when power is initially supplied to the buffer circuit and to turn on the fifth FET momentarily to initially charge the capacitor.