Method for manufacturing a bi-cmos semiconductor device

Abstract

There is provided a method of manufacturing Bi-CMOS semiconductor devices in which further comprises the steps of; depositing a polysilicon layer, an oxide film and a nitride film one and another in order to form the emitter and collector of a bipolar transistor, and the gates of a CMOS; forming an oxide film and a nitride film at the side wall of the polysilicon layer one and another; etching the exposed portions of an epitaxial layer and depositing other nitride film on the nitride film at the side wall; growing an oxide film on the etched portions of the epitaxial layer and removing all the nitride films; and implanting impurities on portions of the epitaxial layer exposed by the etched nitride films in order to make the inactive base region of the bipolar transistor and the source/drain regions of a PMOS transistor P+ type, and to make the source/drain regions of a NMOS transistor n+ type. Accordingly, the widths of the regions can be decreased and thus junction capacitance can be reduced in accordance with the magnitude of the decreased width.