The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 1992
Filed:
Feb. 21, 1992
Charles W Eichelberger, Schenectady, NY (US);
Integrated System Assemblies Corporation, Schenectady, NY (US);
Abstract
Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuation on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block. The connection arrays have interconnection pads which in the final structure are accessible to an external probing device. Specific methods of fabrication are also disclosed.