Logic circuits as for amorphous silicon self-scanned matrix arrays

Abstract

A logic circuit includes pull-up and pull-down transistors and a capacitance, the principal conducting paths of the transistors and the capacitance being coupled in series between a first supply bus and a source of time varying potential. The pull-up transistor is coupled to the capacitance and the capacitance is coupled to the time varying potential. First and second logic signals are applied to the control electrodes of the first and second transistors respectively. The time varying potential is arranged to limit the charge passed by the pull-up transistor permitting use of a relatively small pull-down transistor. The time varying potential has an amplitude sufficiently large to tend to stress the pull-up transistor if such transistor is non conducting. A selectively conductive element (diode) is coupled between a point of clamping potential and the interconnection of the pull-up transistor and capacitance.