The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 1992
Filed:
Aug. 20, 1991
Nobuo Koide, Tokyo, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
One output signal of a D flip-flop circuit FF2 is fed via a wiring W1 back to an input terminal of a D flip-flop circuit FF1, while one output signal of a D flip-flop circuit FF3 is fed via a wiring W2 back to another input terminal of the D flip-flop circuit FF1. One output signal of the D flip-flop circuit FF1 is supplied to an edge-trigger type flip-flop circuit FF4. A NAND circuit NA generates a reset signal in accordance with the output signal of the edge-trigger type flip-flop circuit FF4 and a frequency-dividing switching control signal which changes the frequency-dividing ratio, and sends the reset signal to the D flip-flop circuit FF3. These D flip-flop circuits FF1, FF2, FF3 and FF4 frequency-divide a clock signal by an odd number or an even number. The D flip-flop circuits FF1, FF2, FF3 and FF4 each comprise multiple NOR gates, which each include field-effect transistors. The current-driving performance of the field-effect transistors constituting the NOR gates to which feedback circuits, such as the wirings W1 and W2, are connected as a load, is set almost two to four times that of the field-effect transistors constituting those NOR gates where no feedback circuits are connected.