The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 1992

Filed:

Nov. 04, 1991
Applicant:
Inventor:

Satoshi Hikida, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 57 ; 437 32 ; 148D / ;
Abstract

A method for manufacturing a semiconductor device wherein in the case where a Bi transistor and a CMOS transistor are to be formed on a first conductive semiconductor substrate, a gate oxide film on an active base in a Bi transistor formation region is partially removed by a predetermined pattern so as to form the opening of the gate oxide film, a polysilicon layer having second conductive impurities doped at a high density is patterned over the edge of the opening, and the emitter region of the Bi transistor is formed from the portion in which the active base comes into contact with the first conductive semiconductor substrate, i.e., from the gate edge and the edge of the opening of the gate oxide film to the portion in which the gate oxide film comes into contact with a gate, prior to the steps of determining a transistor formation region by an isolation oxide film, thermally oxidizing the whole surface of the semiconductor substrate including the isolation oxide film, injecting first conductive impurities as the active base in the Bi transistor formation region and forming the polysilicon layer having the second conductive impurities doped at the high density at the gate of the CMOS transistor.


Find Patent Forward Citations

Hikida, Satoshi. (1992). Method for manufacturing a bicmos semiconductor device having a lateral (U.S. Patent No. 5147818). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5147818

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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