The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 1992
Filed:
Apr. 10, 1991
Applicant:
Inventors:
Michael K Ciraula, Manassas, VA (US);
Christopher M Durham, Manassas, VA (US);
Derwin L Jallice, Reston, VA (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
3072963 ; 3072723 ; 307585 ; 307443 ; 36518806 ; 36518911 ; 36518905 ;
Abstract
A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.
Ciraula, Michael. (1992). Glitch-proof powered-down on chip receiver with non-overlapping outputs (U.S. Patent No. 5146111). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5146111
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile