The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1992

Filed:

May. 31, 1989
Applicant:
Inventors:

Dong-Sun Min, Seoul, KR;

Chang-Hyun Kim, Seoul, KR;

Dae-Je Jin, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365226 ; 365227 ;
Abstract

A supply voltage converter circuit for use in reduced geometry high-density semiconductor memory devices, capable of reducing current consumption to as small a value as possible and achieving high-speed operation. The circuit includes a reference voltage generator, for generating a constant reference voltage, and a peripheral power-supply circuit, and array power-supply circuit for providing the internal supply voltage to the peripheral and array circuits, respectively. Each of the peripheral and array power circuits includes a divider, generating a voltage proportional to said internal supply voltage; a main power-supplying part including a main differential amplifier which compares the proportional voltage with said reference voltage and is activated by a given pulse, and a main power component providing the internal source supply voltage in response to output signal of the main differential amplifier; and a sub power supply part including a sub differential amplifier comparing the proportional voltage with the reference voltage, the differential amplifier being at a constant activation state, and a sub power component providing the internal source supply voltage in response to output signal of the sub differential amplifier.


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