Insulated gate field effect transistor with high breakdown voltage

Abstract

An MIS FET has an off-set gate structure in which a gate electrode and a drain region. The drain region is formed of an n type impurity region of a high concentration and has a pn junction region provided between the drain region and the p type silicon substrate. Further, n type impurity regions of the low concentration are in contact with a part of a peripheral portion of the n type impurity regions of the high concentration. The n type impurity regions of the low concentration alleviate the concentration of the electric field near the drain region to increase the drain breakdown voltage. The pn junction region of the n type impurity region of the high concentration and the p type silicon substrate increases a junction capacitance of the entire drain region, increases a surge current discharged to the substrate side from the drain region for the surge breakdown to increase the surge withstanding amount.