Method and system for testing integrated circuits by cycle stealing

Abstract

A system for performing a self test on a circuit without interrupting its normal function. Several embodiments of a self-test system (10, 60, 80, 100, 120) are disclosed, each of which include a test generator (22) that generates a test signal selectively applied to a circuit under test (CUT) (12, 122). The CUT produces an output signal that is analyzed to determine whether the circuit is operating properly. In several of the embodiments, a signature analyzer (44) compares the signature of the output signal to a predetermined expected signature after a sequence of test vectors have been performed on the CUT. In a fault-tolerant embodiment of the self-test system (100), a plurality of CUTs are evaluated in respect to the output signal produced thereby, both when operating to process a normal input signal and, when processing a test signal. A voter (108) selects an output signal for use by a primary signal utilization device (42) from among the output signals of the redundant CUTs and thus determines whether one of the redundant circuits has failed to operate properly. In each embodiment, the self test can occur either during multiple system clock cycles when the circuit is available, or during a portion of each system clock cycle in which the circuit under test is not required to perform its normal function. In another embodiment involving a first circuit portion (124) that produces an intermediate data state that must be held between successive clock cycles for use by a second circuit portion (126), a latch (130) is used to bypass a latch (128) within the circuit under test, so that both portions of the circuit are evaluated without disrupting operation of the signal utilization device.