High-speed differential-feedback cascode sense amplifier

Abstract

A high-speed differential-feedback cascode sense amplifier includes an output stage and a voltage clamp. The voltage clamp is coupled to a pair of bit-sense lines of a memory system or other sense line source. The output stage is coupled to the output of the voltage clamp for generating an output signal having a logic state determined according to the current difference across the bit-sense lines. The voltage clamp includes a pair of transistors (e.g., cascode transistors) in cascode to a differential-feedback gain stage. Bit-sense lines are coupled to the cascode transistors and the differential-feedback gain stage. The gain stage amplifies the current difference across the bit-sense lines to define feedback voltage signals input to the cascode transistors. The parasitic voltage difference across the bit-sense lines resulting from driving the cascode transistors is small, approximately 3-7 mV for an ECL sense amplifier. Because the bit-sense lines are capacitively loaded very heavily, the small parasitic voltage difference across the bit-sense lines enables faster charging/discharging of the bit-sense lines for a memory access. The current difference acros the bit-sense lines is amplified by the gain stage to define feedback voltage signals having a relative voltage difference of approximately 45 milli-Volts. The output of the cascode transistors have a relative voltage difference of approximately 200-400 mV. The output stage further increases the voltage difference to produce two signals, one at each ECL logic state. One of the signal paths forms the sense amplifier output. The addressed memory contents determine whether the signal path for the output is at the logic high level or the logic low voltage level.