The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1992

Filed:

Apr. 17, 1991
Applicant:
Inventors:

Allan T Mitchell, Garland, TX (US);

Bert R Riemenschneider, Murphy, TX (US);

Howard L Tigilaar, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 437 44 ; 437 49 ; 437195 ;
Abstract

An EPROM memory having sidewall floating gates (30) is disclosed. Sidewall floating gates (30) are formed on sidewalls (28) of field insulators (24). Spaced apart bit lines (22), which serve as memory cell sources and drains, are formed. The field insulators (24) overlie the bit lines (22), and sidewall floating gates are formed on the sidewalls (28) of the field insulators (24). In one embodiment, a second set of bit lines (36) is formed between the sidewall floating gates (30), and each memory cell contains one sidewall floating gate (30). In another embodiment, each memory cell contains two sidewall floating gate (30), and the memory cell may be programmed to store from two to four distinct information states.


Find Patent Forward Citations

Mitchell, Allan. (1992). High density eprom fabricaiton method having sidewall floating gates (U.S. Patent No. 5143860). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5143860

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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