The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 1992

Filed:

Mar. 12, 1991
Applicant:
Inventors:

Yasuo Inoue, Hyogo, JP;

Hiroaki Morimoto, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 29 ; 437 21 ; 437 24 ; 437 40 ; 437 83 ; 437 84 ; 437142 ; 437911 ;
Abstract

In a manufacturing method of a junction gate field effect transistor, impurities of a first conductivity type are first implanted at a predetermined concentration into a monocrystal silicon layer separately formed on a region to be used as an active region in an insulating layer, and then surfaces of the monocrystal silicon layer and an insulating substrate are covered with a silicon oxide film. Then, impurities of a second conductivity type are implanted at a predetermined concentration into a portion to be used as a gate electrode in a monocrystal silicon layer by a focused ion beam method, and metal ions are implanted at a predetermined concentration into a portion to be used as a gate electrode of the silicon oxide film covering the monocrystal silicon layer by the focused ion beam method. Then, a polycrystal silicon gate electrode doped with impurities and having an area larger than the portion to be used as the gate electrode of the silicon oxide film is formed to cover a surface of the portion to be used as the gate electrode. Thereafter, impurities of the second conductivity type are implanted at a predetermined concentration into the monocrystal silicon layer, using this polycrystal silicon gate electrode as a mask, to form a source region and a drain region.


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