The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 1992

Filed:

Jan. 22, 1991
Applicant:
Inventor:

Masami Murakata, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 45 ; 357 40 ; 364491 ;
Abstract

An automatic placement method for arranging logic cells on a chip, having a setting step for setting an evaluation function, target values thereof, placement improvement methods, and a range of a satisfaction level of each evaluation function, a calculating step for calculating a difference between a value of each evaluation function and, its target value, an improving step for selecting one of the placement improvement methods to optimize the evaluation function having the largest difference and then executing the placement improvement method; wherein the above processing is repeatedly executed over a required number of times, the range of each evaluation function is set by using probabilistic fluctuation each processing, and the range of each evaluation function is further narrowed with every processing.


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