Chip organization for an extendable memory structure providing busless

Abstract

A memory structure is described as comprised of a large number of fixed-size page frames. Each page frame in the memory is spread among all chips in the memory. The size of the memory structure may be extended or expanded by adding the same type of high-capacity chip originally used to construct the memory. (The chips may be constructed of semiconductor DRAM technology.) When the memory is extended/expanded, the fixed-size page frames have their lateral dimension decreased and their length increased, in accordance with the increase in the number of chips in the memory. A shift register on each chip accommodates the moving of pages within the memory structure as the page-frame shape and the redistribution of the page frame locations in the memory are changed when the number of chips in the memory structure is changed, without requiring any change in the internal structure of the chips. A page of data can be moved in two dimensions between any page frames within the memory structure without using any external bus, even though the size of the memory structure is changed. No bit in a page is moved off of its chip during a page move operation. All bits in a page are accessed and moved logically in parallel. Extremely fast page transfer rates are obtainable by the busless page move operations. Special addressing is provided that accommodates both the internal page move operations and data unit accesses in the memory structure for an external memory bus. Multiple logical memories can be accommodated in the memory structure.