Built-in self test for integrated circuit memory

Abstract

In a built-in self test ('BIST') circuit for on-chip testing of an integrated circuit memory, a control logic circuit is responsive to an external signal on a test select pin for controlling the BIST operations of the major circuit groups thereof. The major circuit groups include an address PRPG (pseudo-random pattern generator), which selectively furnishes test addresses or mission addresses to the memory; a data PRPG, which selectively furnishes test data or mission data to the memory; a PSA (parallel signature analyzer) PRPG, which furnishes mission data from the memory in normal mode and determines a signature in test mode; and a decoder, which compares the signature determined by the PSA PRPG with a known correct signature and sets a flag to indicate memory pass/fail. The BIST circuit is modular and extendable for any N-word by M-bit memory. To this end, a counter in the control logic circuit comprises a plurality of counter slices, the address PRPG comprises a plurality of address slices, the data PRPG comprises a plurality of data slices, and the PSA PRPG comprises a plurality of PSA slices. The BIST circuit is formed by replicating slices for the major circuit groups. Only certain feedback paths in the major circuit groups and certain control signal combinatorial circuits in the control logic require customization.