Arrangements for variable-length encoding and decoding of digital signals

Abstract

Arrangement for variable-length encoding of digital signals, divided into N parallel paths, comprising a routing circuit which, after classification of the encoded signals in accordance with their lengths and classification of the buffer memories in accordance with their filling states, apply those signals to the buffer memories which are less filled as said signals are longer, said routing circuit being arranged between a variable-length encoding circuit and rate control circuit. The corresponding decoding arrangement, which receives said encoded signals in regrouped data blocks accompanied by a respective path indicator for said blocks, comprises, at the output of an inverse quantization circuit, a circuit for routing said blocks as a function of the associated path indicator.