The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 1992
Filed:
May. 17, 1990
Michiyuki Hirata, Kasugai, JP;
Chikai Ono, Kasugai, JP;
Osamu Nomura, Kasugai, JP;
Toru Fukui, Seto, JP;
Susumu Terawaki, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A level conversion circuit includes a level converter and a buffer gate circuit. A level converter includes two pairs of P-channel MOS transistors. A first input signal is supplied to one of the pair of P-channel MOS transistors and a second input signal is supplied to one of the other pair of P-channel MOS transistors. Each of the first and second input signals are complementary ECL-level signals. The buffer gate circuit includes two BiCMOS circuits. A first output signal from one of the pairs of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in one of the BiCMOS circuits. A second output signal from the other pair of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in the other BiCMOS circuit. The first input signal is supplied directly to a gate of a P-channel MOS transistor provided in one the BiCMOS circuits. The second input signal is supplied directly to a gate of a P-channel MOS transistor provided in the other BiCMOS circuit. A first TTL-level output signal is output from one of the circuits, and a second TTL-level output signal is output from the other BiCMOS circuit.