The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 1992
Filed:
Oct. 19, 1990
Shinzou Satou, Kawasaki, JP;
Kou Ebihara, Kawasaki, JP;
Toru Nakamura, Kushikino, JP;
Toshiyuki Koreeda, Sendai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A Bi-CMOS logic circuit includes first and second bipolar transistors connected in series between a first power source and a second power source. An output signal is drawn from a connection node at which first and second bipolar transistors are connected in series. The Bi-CMOS logic circuit also includes a first impedance element, connected between a base and an emitter of the first bipolar transistor, providing a first impedance, and a second impedance element, connected between a base of the second bipolar transistor and an emitter thereof, providing a second impedance. Further, the Bi-CMOS logic circuit includes a first MOS transistor connected between the collector of the first bipolar transistor and the base thereof, a second MOS transistor connected between the collector of the second bipolar transistor and the base thereof, an input signal being applied to gates of the first and second MOS transistors; and a third MOS transistor connected between the base of the first bipolar transistor and the second power source. The third MOS transistor has the gate thereof connected to the base of the second bipolar transistor.