The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 1992

Filed:

Jun. 05, 1991
Applicant:
Inventors:

Amolak Ramde, San Jose, CA (US);

Sheldon Aronowitz, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 24 ; 437 26 ; 437 30 ; 437150 ; 437959 ; 148D / ;
Abstract

A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.


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