The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 1992
Filed:
Jul. 03, 1991
Hiroyuki Kawai, Hyogo, JP;
Hideyuki Terane, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A processing unit containing a DMA controller comprises a 2nb (n.gtoreq.1) processor data bus (6), a 2nb DMA data bus (7), a 2nb (m.gtoreq.1) processor address bus (8), and a 2nb DMA address bus (9). These buses have a plurality of latch circuits (51-54) respectively connected thereto. One of the processor and DMA data latched in each latch circuit, and one of the processor and DMA addresses are selected by a first multiplexer (55, 56). The 2nb data and 2mb data from the output of the first multiplexer and the outputs of the latch circuits are divided into sets of nb and mb, respectively; thus they are given in the form of 3 inputs to a second multiplixer (57-60). When the processor and the DMA controller concurrently operate, data and address are transferred without keeping one of them waiting.