The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 1992

Filed:

Apr. 12, 1990
Applicant:
Inventors:

Naoyuki Morita, Nagano, JP;

Hiroaki Tsugane, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01C / ; H01C / ; H01C / ; H01C / ;
U.S. Cl.
CPC ...
357 40 ; 357 47 ; 357 49 ; 357 52 ; 357 54 ; 437226 ; 437234 ;
Abstract

A semiconductor device wafer in which the interlayer insulating film between wirings and the passivation film formed during the manufacturing process are left on the entire surface of the scribe line area during dicing. The interlayer insulating film between wirings and the passivation film formed during the manufacturing process may be left on most of the scribe line area, in which case a slit groove is provided along the periphery of a chip and the passivation film is removed at the location of the slit groove. Alternatively, the passivation film formed during the manufacturing process may be left on a part of the scribe line area where a film structure is provided. In this case, a slit groove is provided along the periphery of a chip and the passivation film is removed at the location of the slit groove in the same way as mentioned above on the part of the scribe line in which there is a film structure such as an alignment mark, while most of the passivation film on the scribe lines is removed in the area in which there is no film structure.


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