The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 1992
Filed:
Mar. 13, 1991
Applicant:
Inventors:
Michel Pouysegur, Toulouse, FR;
Thierry Parra, Toulouse, FR;
Michel Gayral, Toulouse, FR;
Jacques Graffeuil, Toulouse, FR;
Jean-Francois Sautereau, Toulouse, FR;
Assignee:
Alcatel Espace, Courbevoie, FR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03G / ; H04B / ;
U.S. Cl.
CPC ...
307568 ; 307264 ; 328171 ; 328172 ; 328173 ; 333 172 ;
Abstract
A limiter circuit having a field effect transistor whose bias circuit is constituted by two constant voltage feeds: one for its gate and the other for its drain, with a resistive load being connected in series with the feed to the gate of the transistor. The invention is particularly applicable to space telecommunications.
Pouysegur, Michel. (1992). Limiter circuit having a field effect transistor (U.S. Patent No. 5136193). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5136193
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile