The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 1992
Filed:
Oct. 31, 1990
Chuck D Khuat, Tulsa, O;
Seiscor Technologies Inc., Tulsa, OK (US);
Abstract
A telephone interface circuit for use in a digital loop carrier system. A transformer for coupling analog information and a switch responsive to a hook condition signal is provided. The hook condition signal provides an indication of the 'on/off hook' condition of a corresponding telephone subscriber. The switch provides a closed circuit condition to 'sink' a DC current when the corresponding telephone subscriber is 'off hook' and an open circuit condition when the corresponding subscriber is 'on hook'. The telephone interface circuit further includes a capacitor serially coupled with the primary winding of the transformer, to prevent DC current from passing through the primary winding of the transformer. A combination telephone interface circuit that can be adapted for use as a remote terminal interface circuit or as a central office terminal interface circuit is also included. The combination interface circuit includes first and second circuit paths disposed in parallel with each other. The first circuit path includes a transformer, switch, and capacitor as described above. The second circuit path includes a subscriber line interface circuit. The combination interface circuit includes jumper wires for selectively coupling either the first circuit path or the second circuit path between a pair of input teriminals and a pair of output terminals of the combination interface circuit.