Shift register circuit

Abstract

A shift register circuit includes a logical operator which is added to an output terminal of a latch portion and takes a logical operation of input and output signals of the latch portion and outputs its result as a bit signal. The signal of a bit component is shifted to a higher order bit every half of the period of a clock signal so that a shifting speed thereof can be made two times faster than that in a conventional shift register circuit. It may be arranged such that a higher order bit section starts to output a signal after the preceding lower order bit section outputs a low level signal thereby enabling to avoid the signals outputted by the bit sections neighboring to each other becoming simultaneously intermediate values between a high level and a low level. Also, the bit sections may be cascade-connected such that each of the sections takes a logical operation of the input and output signals of the latch portion. In view of the configuration involved, the number of elements per bit can be reduced.