The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 1992

Filed:

Nov. 06, 1989
Applicant:
Inventor:

John R Obermeyer, Campbell, CA (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
371 211 ; 371 212 ;
Abstract

A system for testing a RAM array bus transaction buffer without halting system operation or using a special protocol, including a RAM control selection circuit for providing to the RAM either a set of normal control, data and address signals or diagnostic control, data and address signals; a Diagnostics Mode Bit Register (DMBR); a Diagnostics Address Register (DAR); and means for recognizing instructions to write to those registers or to a fictitious Diagnostics Data Register (DDR). First a normal write operation is executed to the DMBR, to control a RAM control selection circuit. The RAM control selection circuit chooses as RAM control signal sources a set of diagnostic sources rather than normal system sources. Second, a selected RAM address is written to the DAR. Third, a write operation is performed to the DDR, causing the selected data to be written to the RAM at the address specified by the DAR. Data is similarly read from the RAM through the DDR.


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