Semiconductor memory device having on-chip test circuit and operating

Abstract

Same test data is written into corresponding memory cells of each subarray of a memory cell array to be read out. A comparing and determining circuit determines whether the data read out from each memory cell has the same logic or not, and the data proves defective when any one of the data has different logic. An output of the comparing and determining circuit is stored in a register to be externally outputted through a predetermined pin (e.g. output enable pin). Timing in which the register accepts the data stored in the comparing and determining circuit is controlled by a switching controlling signal generating circuit disposed in a semiconductor memory device. As the above, all signals necessary for a test are generated in the semiconductor memory device, and the test result is outputted through an existing pin, so that it is structured by the same number of pins as that of a standard semiconductor memory device without a testing function.