The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 1992
Filed:
Nov. 13, 1989
Edwin A Kelley, Los Angeles, CA (US);
Howard H Baller, Marina del Rey, CA (US);
Randall L Conilogue, Thousand Oaks, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each stage of each adder has a first full adder and a second full adder. Each full adder has an addend input, an augend input, a carry input, a sum output, and a carry output. In the first adder, the first source is connected to the addend input of the first full adder, the second source is connected to the augend input of the first full adder, the third source is connected to the carry input of the first full adder, the sum output of the first full adder is connected to the addend input of the second full adder, the carry output of the first full adder is connected to the carry input of the next higher order stage of the second full adder, and the fourth source is connected to the augend input of the second full adder. The full adders are implemented with low-level, non-saturating, bipolar differential logic circuitry, which greatly reduces the power dissipation at high data processing speeds. The circuitry is physically laid out on an integrated circuit chip so the stages within an adder are contiguous to each other in bit order and/or the corresponding stages of different adders are aligned with each other.