High speed passgate, latch and flip-flop circuits

Abstract

A BICMOS passgate circuit (PSGT3) (PSGT3A) for use in latches and flip-flops incorporates a bipolar output circuit (Q1,Q3) comprising a bipolar pullup transistor element (Q1) and a bipolar pulldown transistor element (Q3) coupled to the passgate output (V.sub.OUT) for transient charging and discharging of load capacitance (C.sub.L) at the passgate output (V.sub.OUT). The bipolar output circuit provides increased sinking and sourcing output drive current and .beta. amplification of sinking and sourcing drive current at the passgate output V.sub.OUT in response to data signals at the passgate intput (V'.sub.IN) in the transparent operating mode. An MOS input logic circuit coupled to the passgate input (V'.sub.IN) includes clock signal inputs (CP,CP) for implementing transparent and blocking operating modes. The MOS input logic circuit (QP3,QP4,QP5,QP6, NAND1) is coupled to the bipolar output circuit (Q1,Q3) and is constructed to control the conducting states of the bipolar pullup (Q1) and pulldown (Q3) transistor elements for transient turn on of one of the respective bipolar pullup and pulldown transistor elements during respective switching transitions at the passgate output (V.sub.OUT). The MOS input logic circuit is also constructed for turn off of the bipolar pullup (Q1) and pulldown (Q3) transistor elements follow switching transitions at the output (V.sub.OUT) and during the blocking operating mode. A final latchback circuit (LTBK2) (INV3,INV4) is coupled to the passgate output to latch an output data signal and for pulling up the final output (V.sub.OUT) to a high potential level power rail (V.sub.cc).