The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 1992
Filed:
Nov. 27, 1990
Yoshihiro Tsuru, Kodaira, JP;
Takashi Kuraishi, Takasaki, JP;
Fumiaki Matsuzaki, Takasaki, JP;
Takaharu Morishige, Takasaki, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Microcomputer System Ltd., Tokyo, JP;
Abstract
A semiconductor gate array device compatible with ECL and/or TTL, wherein the input buffer unit includes a TTL input stage, an ECL input stage and a common output stage, and the output buffer unit includes a common input stage, an ECL output stage and a TTL output stage. When the device is to be used as a TTL input interface, the TTL input stage and the common output stage are coupled together and when the device is to be used as an ECL input interface, the ECL input stage and the common output stage are coupled together. When used as a TTL output interface, the common input stage and the TTL output stage are coupled together and when used as an ECL output interface, the common input stage and the ECL output stage are coupled together. Therefore, the input/output interfaces exhibit general applicability to meet the user's demands, yet enabling the layout areas of the input and output buffer portions to be decreased.