The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 1992
Filed:
Dec. 14, 1990
Jeffrey R Murphy, Rocklin, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A network bridge with a three port interface to random access memory is presented. The network bridge includes a system processor, a random access memory, a first memory access controller, a second memory access controller and a three port interface to the random access memory. The random access memory is used to store data packets received by the network bridge from the first network and the second network. The three port interface to the random access memory includes a first port connected to the first memory access controller, a second port connected to the second memory access controller and a third port connected to the system processor. The three port interface allots to the first memory access controller, to the second memory access controller and to the system processor access to the random access memory. The access to the random access memory is allotted so that the first memory access controller, the second memory access controller and the system processor all have equal access priority. The three port interface access cycle is approximately three time as fast as the access cycle of the system processor, the first memory access controller and the second memory access controller. This eliminates the need for local buffers between the memory access controllers and the networks and allows the system processor and the memory access controllers to access the three port interface simultaneously with a minimum of access collisions.