The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 1992

Filed:

Jun. 14, 1991
Applicant:
Inventors:

Jean-Philippe Blanc, Gieres, FR;

Joelle Bonaime, Echirolles, FR;

Jean du De Poncharra, Quaix-en-Chartreuse, FR;

Robert Truche, Gieres, FR;

Assignee:

Brevatome, Paris, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 23700 ; 357-4 ; 357 55 ; 357 50 ; 357 59 ; 357 38 ; 357 39 ;
Abstract

An integrated circuit in silicon on insulator technology comprises a JFET transistor with an insulated source and drain of one conductivity type in the upper part of a semiconductor island, an upper gate between the source and the drain, a buried insulating layer supporting the island, and a buried electrode in the island and in contact with the insulating layer. That electrode has a second conductivity type different from the first. A zone is diffused into at least one edge of the island from a conductive material covering the edge, that conductive material being doped with impurities of the second conductivity type. The diffused zone of the second conductivity type is electrically insulated from the source and drain and ensures the electrical contacting of the electrode and the conductive material constituting the electrical contact to the electrode and source. Drain and gate contacts are also provided which are electrically insulated from one another and from the electrode contact. A process for making the circuit is also disclosed.


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