Compact, high-density packaging apparatus for high performance

Abstract

A compact high-density packaging arrangement for high-performance semiconductor devices includes a plurality of high-performance semiconductor chips connected to a multilayer daughter substrate member using a bare chip assembly technique known as bonded pin technology. Internal bonded pins are formed on bonding pads of the chips and soldered to conductive pads in solder wells located on the daughter substrate to provide a first level of interconnection for the chips. A larger, multilayer mother substrate member has a plurality of apertures formed in one surface thereof. These apertures are terminated by a top side of a metallized base layer of the substrate. An opposite surface of the mother substrate, i.e. a bottom side of the base layer, is affixed in thermal conductive relation to a metallic cold plate adapted for receiving a cooling fluid. External bonded pins are formed on bonding pads of the daughter substrate and inserted into corresponding solder wells located on the mother substrate. Concurrently, the bare chips are situated into the apertures in intimate thermal conductive relation to the cold plate via the metallized base layer. The pins are then soldered to conductive pads in the solder wells, thereby providing a second level of chip interconnection when other chip-populated daughter substrates are mounted thereon.